1. Technical Field
The disclosed embodiments relate to time-to-digital converters (TDCs).
2. Background Information
A time-to-digital converter (TDC) is a circuit that produces a digital output value (sometimes referred to as a timestamp). The timestamp represents the time elapsed between an edge of a first signal and an edge of another signal. TDCs have several uses including uses in phase-locked loops (PLLs).
FIG. 1 (Prior Art) is a high level simplified conceptual block diagram of a TDC PLL 1. TDC PLL 1 involves a loop filter 2 that outputs a stream of multi-bit digital tuning words. A Digitally Controlled Oscillator (DCO) 3 receives a digital tuning word and outputs a corresponding signal DCO_OUT whose frequency is determined by the digital tuning word. DCO_OUT may, for example, have a frequency in the range of three to four GHz. An accumulator 4 increments each period of DCO_OUT, and the value of the accumulator is latched into latch 5 synchronously with a reference clock signal REF. A reference phase accumulator 6 increments by the value on its input leads 7. Reference phase accumulator 6 increments synchronously with reference clock signal REF. The value accumulated in accumulator 6 is supplied via lines 8 to a subtractor 9. The output of an adder 10 is supplied via lines 11 to subtractor 9. Subtractor 9, which is also referred to as a phase detector, subtracts the value on lines 11 from the value on lines 8 and supplies the resulting difference in the form of a digital word on lines 12 to loop filter 2.
The value on input leads 7 by which accumulator 6 increments is the sum of an integer frequency control portion on lines 13 and a fractional portion on lines 14. The fractional portion is changed over time by a delta-sigma modulator 15. The value on lines 11 is the sum of an integer portion output by latch 5 as well as a fractional portion on lines 16. A time-to-digital converter 17 produces a digital output timestamp representing the time difference between an edge of the signal DCO_OUT and an edge of the reference clock signal REF. The signal REF in this example has a fixed, but significantly lower frequency than DCO_OUT. The timestamps output by TDC 17 are normalized by a normalization circuit 18 to generate the fractional portion on lines 16.
FIG. 2 (Prior Art) is a simplified diagram of TDC 17. TDC 17 includes a delay line of inverters 19-23, and an associated set of flip-flops 24-28. A wave front of the DCO_OUT signal propagates down the delay line of inverters and when the rising edge of the reference clock signal REF occurs, the state of the signal in the delay line is clocked in parallel into flip-flops 24-28. The flip-flops output a multi-bit digital word referred to here as a “timestamp” onto lines 29.
FIG. 3 (Prior Art) is a simplified waveform diagram that illustrates an operation of TDC 17. One low pulse is captured within, and is propagating through, the delay line. The row of ones and zeros 30 represents the values on the various nodes of the delay line. When the DCO_OUT low pulse reaches the position in the delay line illustrated in FIG. 3, the signal REF transitions from low-to-high. The amount of time that elapsed between the time of the low-to-high edge of the end of the low pulse of DCO_OUT and the time of the low-to-high transition of REF is identified as time PD. The duration of time that the DCO_OUT signal remained low (half-cycle time) is identified as time HPER. If the inverters of the delay line have small propagation times (the inverters are “fast”), then the state of the signals on the nodes of the delay line might appear as indicated by row 30. PD is equal to approximately seven inverter propagation delays and HPER is equal to approximately eight inverter propagation delays. The value PD here is indicative of the time delay between the low-to-high edge of DCO_OUT and the low-to-high edge of REF. The unit of time measurement is inverter propagation delay. The TDC PLL uses this phase information to keep the TDC PLL in lock.
If, however, the inverters of the delay line have larger propagation times (the inverters are “slow”), then the state of the signals on the nodes of the delay line might appear as indicated by row 31. Rather than the value PD that indicates the duration of the time between the low-to-high edge of DCO_OUT and the low-to-high edge of REF being seven, the value PD is four. Similarly, rather than the value HPER being eight, the value HPER is four. It is desired that the timestamp as output from the TDC be normalized so that it is less dependent on propagation speed changes of the inverters of the delay line.
FIG. 4 (Prior Art) is a simplified circuit diagram of normalization circuit 18 of FIG. 1. Normalization circuit 18 receives the non-normalized timestamp value PD output from TDC 17, normalizes it using multiplier 38, and outputs a normalized timestamp value PDN onto lines 16. The normalization circuit 18 uses the HPER values output from TDC 17 to perform the normalization. The four-bit values HPER are supplied on lines 32 to an accumulator 33. Accumulator 33 increments by the value HPER on each rising edge of a much slower reference clock CKR. Accordingly if the value HPER is small, then it will take more increments of accumulator 33 for accumulator 33 to overflow and to output an overflow signal on line 34. If, however, the value HPER is large, then it will take comparatively fewer increments of accumulator 33 for the overflow condition to occur. The number of times accumulator 33 is incremented is recorded by counter 35. When the overflow condition occurs, the overflow signal on line 34 transitions high and causes latch 36 to store the count value from counter 35. Accordingly, if HPER is small, then the count value captured will be larger, whereas if HPER is large, then the count value captured will be smaller. The count value AVE_PER is supplied by lines 37 to multiplier 38. If HPER is small, then PD will be small as well, but multiplier 38 will multiply this small PD value by a larger AVE_PER thereby outputting the normalized PDN. Similarly, if HPER is large, then PD will be large as well, but multiplier 38 will multiply this large PD value by a smaller AVE_PER thereby outputting the normalized PDN.
A PLL such as TDC PLL 1 of FIGS. 1-4 sees use in many applications including in radio receivers and in radio transmitters. Improvement of the performance of the TDC PLL is desired.